Portál AbcLinuxu, 9. srpna 2025 08:31
$ cat x86info #!/bin/sh cat /proc/cpuinfo $_
x86info v1.21. Dave Jones 2001-2007 Feedback to <davej@redhat.com>. Found 1 CPU, but found 2d CPUs in MPTable. MP Table: # APIC ID Version State Family Model Step Flags # 0 0x 7 BSP, usable 27 15 15 0x1a00c035 # 0 0x 0 AP, unusable 0 0 10 0x78ffff0a -------------------------------------------------------------------------- eax in: 0x00000000, eax = 00000001 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x00000001, eax = 000006a0 ebx = 00000000 ecx = 00000000 edx = 0383fbff eax in: 0x80000000, eax = 80000008 ebx = 68747541 ecx = 444d4163 edx = 69746e65 eax in: 0x80000001, eax = 000007a0 ebx = 00000000 ecx = 00000000 edx = c1c3fbff eax in: 0x80000002, eax = 20444d41 ebx = 6c687441 ecx = 74286e6f edx = 5820296d eax in: 0x80000003, eax = 32332050 ebx = 002b3030 ecx = 00000000 edx = 00000000 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 eax in: 0x80000005, eax = 0408ff08 ebx = ff20ff10 ecx = 40020140 edx = 40020140 eax in: 0x80000006, eax = 00000000 ebx = 41004100 ecx = 02008140 edx = 00000000 eax in: 0x80000007, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000001 eax in: 0x80000008, eax = 00002022 ebx = 00000000 ecx = 00000000 edx = 00000000 Family: 6 Model: 10 Stepping: 0 CPU Model : Athlon XP (Barton) Feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse Extended feature flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmxext mmx fxsr 3dnowext 3dnow /dev/cpu/0/msr: No such file or directory Couldn't read MSR 0x2a Couldn't read MSR 0xc0000080 Couldn't read MSR 0xc0010010 Couldn't read MSR 0xc0010015 Couldn't read MSR 0xc001001b L1 Data TLB (2M/4M): 4-way associative. 8 entries. L1 Instruction TLB (2M/4M): Fully associative. 8 entries. L1 Data TLB (4K): Fully associative. 32 entries. L1 Instruction TLB (4K): Fully associative. 16 entries. L1 Data cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L1 Instruction cache: Size: 64Kb 2-way associative. lines per tag=1 line size=64 bytes. L2 Data TLB (2M/4M): Disabled. 0 entries. L2 Instruction TLB (2M/4M): Disabled. 0 entries. L2 Data TLB (4K): 4-way associative. 256 entries. L2 Instruction TLB (4K): 4-way associative. 256 entries. L2 cache: Size: 512Kb 16-way associative. lines per tag=1 line size=64 bytes. PowerNOW! Technology information Available features: Temperature sensing diode present. Address Size: 32 bits virtual, 34 bits physical Connector type: Socket A (462 Pin PGA) MTRR registers: MTRRcap (0xfe): MTRRphysBase0 (0x200): MTRRphysMask0 (0x201): MTRRphysBase1 (0x202): MTRRphysMask1 (0x203): MTRRphysBase2 (0x204): MTRRphysMask2 (0x205): MTRRphysBase3 (0x206): MTRRphysMask3 (0x207): MTRRphysBase4 (0x208): MTRRphysMask4 (0x209): MTRRphysBase5 (0x20a): MTRRphysMask5 (0x20b): MTRRphysBase6 (0x20c): MTRRphysMask6 (0x20d): MTRRphysBase7 (0x20e): MTRRphysMask7 (0x20f): MTRRfix64K_00000 (0x250): MTRRfix16K_80000 (0x258): MTRRfix16K_A0000 (0x259): MTRRfix4K_C8000 (0x269): MTRRfix4K_D0000 0x26a: MTRRfix4K_D8000 0x26b: MTRRfix4K_E0000 0x26c: MTRRfix4K_E8000 0x26d: MTRRfix4K_F0000 0x26e: MTRRfix4K_F8000 0x26f: MTRRdefType (0x2ff): 2.20GHz processor (estimate).
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